library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity fenpin_2 is
port(clk:in std_logic;
data:in std_logic_vector(7 downto 0);
q:out std_logic);
end fenpin_2;
architecture one of fenpin_2 is
signal data1,data2:std_logic_vector(7 downto 0);
signal data3,data4:std_logic_vector(7 downto 0);
signal q1,q2,q3:std_logic;
begin
data1<=data-1;
data2<='0'&data1(7)&data1(6)&data1(5)&data1(4)&data1(3)&data1(2)&data1(1)when data(0)='1' else
'0'&data(7)&data(6)&data(5)&data(4)&data(3)&data(2)&data(1);
process(clk)
begin
if clk'event and clk='1' then
if data3<data1 then
data3<=data3+1;
else data3<="00000000";
end if ;
end if;
end process;
process(clk)
begin
if clk'event and clk='0' then
if data4<data1 then
data4<=data4+1;
else data4<="00000000";
end if ;
end if;
end process;
process(data3,data2)
begin
if(data3<data2) then
q1<='1';
else q1<='0';
end if ;
end process;
process(data4,data2)
begin
if(data4<data2) then
q2<='1';
else q2<='0';
end if ;
end process;
process(q1,q2)
begin
q3<=q1 or q2;
end process;
q<= clk when data="00000001" else
q3 when data(0)='1' else
q1;
end one ;
